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| Ordering number : ENA0646 Monolithic Linear IC LA73033M Overview I2C bus control (excluding standby control and RGB through control) This LA73033M is DVD recorder video signal input SW & output driver. Functions [SW side] * Composite signal five-input SW and S signal three-input SW * Keyed clamp * Component signal or RGB signal 1 input * 0dB/ 6dB amplifier * AGC amplifier (composite and Y signal only) * LPF for removal of 13.5MHz clock * Composite output/ Y output changeover switch * Compatible with standby (two types) * C.SYNC & V.SYNC output [Driver side] * Six-channel input & six-channel output of composite signal & S signal & component or RGB signal * Clamp (keyed clamp for Cb and Cr) * 6dB/ 9dB amplifier amplifier * LPF for removal of 27MHz/ 54MHz clock * Output mute (three types) * 75 driver (two drives possible) * Through changeover of RGB signal from the SW side * Y/ C-MIX * DC output for S1/ S2 * SCART-RGB/ YC changeover SW Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. 71807 TI PC B8-7592, No.0646-1/24 LA73033M Specifications Maximum Ratings at Ta = 25C Parameter Maximum supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VCC max Pd max Topg Tstg Ta 75C * Mounted on a board Conditions Ratings 7.0 1200 -20 to +75 -40 to +150 Unit V mW C C * Mounted on a board : 114.3x76.1x1.6mm3, glass epoxy board. Recommended Operating Conditions at Ta = 25C Parameter Recommended supply voltage Operating supply voltage range Input pin voltage application range Symbol VCC VCC opg VIN VCC opg +0.3 7V Conditions Ratings 5.0 4.75 to 5.25 -0.3 to VCC opg +0.3 Unit V V V Package Dimensions unit : mm (typ) 3255 17.2 60 61 41 40 80 1 (0.83) 0.65 0.25 20 21 0.15 3.0max 0.1 (2.7) SANYO : QFP80(14X14) 14.0 17.2 0.8 14.0 No.A0646-2/24 Electrical Characteristics at Ta = 25C, VCC = 5.0V Out Test Condition min Current flowing through VCC1 at no signal Current flowing through VCC1 at standby control VCC1 control 1Vp-p voltage) T27 Measure the output clamp voltage (sink chip 0.7 0.8 0.9 V 330 0 0 3.5 01001010 01101010 10001010 10101010 11001010 714mVp-p T25 voltage) Measure the output DC voltage (center 2.2 2.4 2.7 V 330 0 0 3.5 01000100 01100100 10000100 1Vp-p voltage) T27 Measure the output clamp voltage (sink chip 0.7 0.8 0.9 V 330 0 0 3.5 01000100 01100100 10000100 1Vp-p 1Vp-p 1Vp-p 700mVp-p T23 700mVp-p T25 1Vp-p 700mVp-p T29 1Vp-p 714mVp-p T25 1Vp-p 700mVp-p T23 700mVp-p T25 1Vp-p 700mVp-p T29 Continued on next page. T27 T27 0 0 3.5 T27 Measure GAIN for input of each output 5.5 6 6.5 dB 330 0 0 3.5 01001010 01000100 01001000 00101100 00000000 00000000 00000000 00000000 Measure the output pedestal clamp voltage T25 1.15 1.25 1.35 V 330 0 0 3.5 00100100 00000000 T23 Measure the output pedestal clamp voltage 2.4 2.5 2.6 V 330 0 0 3.5 00000100 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Current flowing through VCC1 at EXT-RGB 11 14 17 mA 330 3 3 9 11 13 mA 330 3 0 58 73 88 mA 330 0 0 3.5 01000010 typ max R1 V18 V38 V30, V35 SW1 unit Mag VCC1 VCC1 Point Spec Control voltage I C bus data (MSB-LSB) SW2 00000000 2 Parameter Freq Symbol Input signal Point Signal Current drain 1 ICC11 Current drain at standby ICC12 Current drain 1 at RGB ICC13 standby Composite output clamp C23 SG3 voltage VIN13 VIN15 VIN17 VIN19 VIN21 Chroma output center C25 SG2 voltage VIN7 VIN5 VIN3 Y output clamp voltage C27 VIN79 SG1 LA73033M VIN77 VIN75 Component output pedestal SG5 voltage PC23 VIN1 VIN11 SG6 PC25 VIN9 SG6 RGB output clmap voltage RC23 SG8 RC25 VIN11 VIN9 SG8 SG5 RC29 VIN1 VIN73 SG8 Gain at 6dB G23H SG5 G25H VIN13 VIN7 SG6 G27H VIN79 SG5 G23H SG8 G25H VIN11 VIN9 SG8 G27H SG5 No.A0646-3/24 G29H VIN1 VIN73 SG8 Continued from preceding page. Out Test Condition min Measure GAIN for input of each output 01000010 01000000 01000000 00100000 -0.5 0 0.5 dB 330 0 0 3.5 typ max R1 V18 V38 V30, V35 SW1 unit Mag 2Vp-p 1.428Vp-p T25 2Vp-p 1.4Vp-p 1.4Vp-p 2Vp-p 1.4Vp-p 1Vp-p 1Vp-p 10MHz T27 calculates the change rate for gain at 100kHz. T27 10MHz 714mVp-p T25 10MHz 10MHz 700mVp-p T23 10MHz 700mVp-p T25 10MHz 10MHz 700mVp-p T29 4.5MHz 4.5MHz 714mVp-p T25 4.5MHz 4.5MHz 700mVp-p T23 4.5MHz 700mVp-p T25 4.5MHz 4.5MHz 700mVp-p T29 5MHz 5MHz 5MHz 5MHz 5MHz 5MHz 5MHz 700mVp-p T29 Continued on next page. 1Vp-p T27 700mVp-p T25 700mVp-p T23 1Vp-p T27 714mVp-p T25 1Vp-p T27 Measure gain for input of each output and calculates the change rate for gain at 100kHz. -1 -0.3 0.5 dB 1k 0 0 3.5 01011010 01010100 01011000 00111100 00000000 00000000 00000000 00000000 1Vp-p T27 1Vp-p T27 calculates the change rate for gain at 100kHz. 1Vp-p T27 Measure gain for input of each output and -0.5 -0.2 0.5 dB 1k 0 0 3.5 01011010 01010100 01011000 00111100 00000000 00000000 00000000 00000000 1Vp-p T27 1Vp-p 1Vp-p Measure gain for input of each output and -0.5 -0.1 0.5 dB 330 0 T27 changeable. 0 T27 Measure V30 and V35 where the output gain 2 3.5 5 V 330 0 0 T29 VA23M VA27M 3.5 01001010 01001000 01001010 01000100 01001000 00101100 10000000 10000000 00000000 00000000 00000000 00000000 T27 T25 T23 T27 T27 Point Spec Control voltage I C bus data (MSB-LSB) SW2 00000000 00000000 00000000 00000000 2 Parameter Freq Symbol Input signal Point Signal Gain at 0dB G23L SG5 G25L VIN13 VIN7 SG6 G27L VIN79 SG5 G23H SG8 G25H VIN11 VIN9 SG8 G27H SG5 G29H VIN1 VIN73 SG8 AGC-AMP control voltage VA23M SG5 VA27M VIN13 VIN79 SG5 10MHz change rate for F23 SG3 f characteristics of gain F25 VIN13 VIN7 SG2 F27 VIN79 SG1 F23 SG9 F25 VIN11 VIN9 SG9 F27 SG1 F29 VIN1 VIN73 SG9 LA73033M 4.5MHz change rate of F23L1 SG3 f characterics of gain F25L1 VIN13 VIN7 SG2 (with LPF) F27L1 VIN79 SG1 F23L1 SG9 F25L1 VIN11 VIN9 SG9 F27L1 SG1 F29L1 VIN1 VIN73 SG9 5MHz change rate of F23L2 SG3 f characterics of gain F25L2 VIN13 VIN7 SG2 (with LPF) F27L2 VIN79 SG1 F23L2 SG9 F25L2 VIN11 VIN9 SG9 F27L2 SG1 No.A0646-4/24 F29L2 VIN1 VIN73 SG9 Continued from preceding page. Out Test Condition min Measure gain for input of each output and calculates the change rate for gain at 100kHz. 01010100 01011000 00111100 -41 -30 dB 1k 0 0 3.5 01011010 typ max R1 V18 V38 V30, V35 SW1 unit Mag 1Vp-p 1Vp-p T27 T27 Point Spec Control voltage I C bus data (MSB-LSB) SW2 00000000 00000000 00000000 00000000 2 Parameter Freq 13.5MHz 13.5MHz 714mVp-p T25 13.5MHz 13.5MHz 700mVp-p T23 13.5MHz 700mVp-p T25 13.5MHz 13.5MHz 700mVp-p T29 5MHz Connect the load of 330 to the output via C connection and measure the secondary distortion of output. -45 -35 dB 330 0 5MHz 5MHz 5MHz 5MHz 5MHz 5MHz 5MHz 5MHz 5MHz 5MHz 5MHz 5MHz 5MHz 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p T37 Connect 10k between this output and VCC. 0 0.3 0.6 V 0 0 3.5 T37 Connect 10k between this output and VCC. 4.75 5 5.25 V 0 0 3.5 T36 Connect 10k between this output and VCC. 0 0.3 0.6 V 0 0 3.5 T36 700mVp-p T29 Connect 10k between this output and VCC. 4.75 5 5.25 V 0 0 3.5 01001010 01001000 01001010 01001000 01001010 01001000 01001010 01001000 1Vp-p T27 700mVp-p T25 700mVp-p T23 1Vp-p T27 distortion of output. 714mVp-p T25 connection and measure the secondary 1Vp-p T27 Connect the load of 1k to the output via C -45 -35 700mVp-p T29 dB 330 0 0 3.5 01011010 01010100 01011000 00111100 1Vp-p T27 700mVp-p T25 700mVp-p T23 1Vp-p T27 714mVp-p T25 1Vp-p T27 0 3.5 01001010 01000100 01001000 00101100 1Vp-p T27 Symbol Input signal Point Signal 13.5 MHz change rate of F23L3 SG3 f characteristics of gain F25L3 VIN13 VIN7 SG2 (with LPF) F27L3 VIN79 SG1 F23L3 SG9 F25L3 VIN11 VIN9 SG9 F27L3 SG1 F29L3 VIN1 VIN73 SG9 Output drive capacity 1 H23 SG3 00000000 00000000 00000000 00000000 (secondary distortion) H25 VIN13 VIN7 SG2 H27 VIN79 SG1 H23 SG9 H25 VIN11 VIN9 SG9 H27 SG1 H29 VIN1 VIN73 SG9 Output drive capacity 1 H23 SG3 00000000 00000000 00000000 00000000 (secondary distortion) H25 VIN13 VIN7 SG2 LA73033M (with LPF) H27 VIN79 SG1 H23 SG9 H25 VIN11 VIN9 SG9 H27 SG1 H29 VIN1 VIN73 SG9 C.SYNC output H voltage V36H VIN13 SG5 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Continued on next page. VIN79 SG5 C.SYNC output L voltage V36L VIN13 SG5 VIN79 SG5 C.SYNC2 output H voltage V37H SG5 VIN13 VIN79 SG5 C.SYNC2 output L voltage V37L SG5 VIN13 VIN79 No.A0646-5/24 SG5 Continued from preceding page. Out Test Condition min Output pulse width 01001000 T36 pulse width becomes 1.3-folds or more as the input SYNC is reduced. The value of input SYNC at which the output 7.5 11.5 15.5 IRE 0 0 3.5 01001010 01001000 3.2 4.2 5.2 s 0 0 3.5 01001010 typ max R1 V18 V38 V30, V35 SW1 unit Mag 1Vp-p 1Vp-p 1Vp-p 1Vp-p T36 Point Spec Control voltage I C bus data (MSB-LSB) SW2 00000000 00000000 00000000 00000000 2 Parameter Freq Symbol Input signal Point Signal C.SYNC output pulse width W36 VIN13 SG5 VIN79 SG5 C.SYNC threshold level W36V VIN13 SG5 VIN79 SG5 (Note) The C. SYNC2 threshold level is 12 IRE at 6dB and 12.8 IRE at 0dB . Design guarantee items Out Test Condition min Ratio of the amplitude on the white level relative to that on the black level. When AGC amplifier is used -2 1 2 % VA23M VA27M Difference of the phase on the white level relative to that on the black level When AGC amplifier is used -1 1.2 2 deg VA23M VA27M The magnitude of crosstalk in which the non-selected input signal is carried on the T25 of selected signal output. T27 -60 -55 dB 330 0 0 3.5 01001000 00000000 selected signal output is specified by the value -60 -55 dB 330 0 0 3.5 01000100 00000000 -60 -55 dB 330 0 0 3.5 -1 1 1.5 deg 1k 0 0 3.5 -2 1 2 % 1k typ max R1 unit 0 Mag 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 4MHz 4MHz 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p T27 T27 T27 T27 S/ N in the HPF100kHz and LPF 10MHz bands is expressed in dB. S/ N in the HPF100kHz and LPF 10MHz bands is expressed in dB. -65 -60 dB 1k 0 0 3.5 -70 -65 dB 330 0 0 3.5 01001010 01001000 01011010 01011000 00000000 00000000 00000000 00000000 714mVp-p 714mVp-p T27 T27 T27 T27 T27 T27 T27 T27 T27 Point Spec Control voltage V18 V38 V30, V35 0 3.5 I C bus data (MSB-LSB) SW1 01011010 01011000 01011010 01011000 01011010 01011000 01011010 01011000 01001010 SW2 00000000 00000000 10000000 10000000 00000000 00000000 10000000 10000000 00000000 2 Parameter Freq 3.58MHz 3.58MHz 3.58MHz 3.58MHz 3.58MHz 3.58MHz 3.58MHz 3.58MHz Symbol Input signal Point Signal DG DG23 SG7 DG27 VIN13 VIN79 SG7 ADG23 SG7 ADG27 VIN13 VIN79 SG7 DP DP23 SG7 LA73033M DP27 VIN13 VIN79 SG7 ADP23 SG7 ADP27 VIN13 VIN79 SG7 Crosstalk CT23 SG5 VIN13 VIN15 SG5 CT25 SG2 VIN7 VIN5 SG2 CT27 SG5 VIN79 VIN77 SG5 Video S/ N ratio SN23 SG5 SN27 VIN13 VIN79 SG5 Video S/ N ratio SN23 SG5 (with LPF) SN27 VIN13 VIN79 SG5 No.A0646-6/24 Electrical characteristics at Ta=25C, unless otherwise specified VCC = 5.0V Spec Control max V18 Current flowing through VCC2 at no signal Current flowing through VCC2 at EXT-RGB control 1Vp-p Measure gain of each output relative to input 5.6 5.9 6.4 dB 0 0 ON 714mVp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 709mVp-p Measure gain of each output relative to input 8.55 8.9 9.45 dB 0 507mVp-p 709mVp-p 709mVp-p 709mVp-p 709mVp-p 1Vp-p 714mVp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 709mVp-p 507mVp-p 709mVp-p 709mVp-p 709mVp-p 709mVp-p 709mVp-p 507mVp-p 709mVp-p T63 Continued on next page. T65 T68 T56 Calculate the gain ratio of two outputs. -5 0 5 % 0 0 ON ON 00000000 11110000 T58 T60 T63 T65 T68 Measure gain of each output relative to input T56 8.55 9.1 9.45 dB 0 0 ON OFF 00000000 11110000 T58 T60 T63 T65 T68 Measure gain of each output relative to input 5.6 6.1 T56 6.4 dB 0 0 OFF ON 00000000 00110000 T58 T60 T63 T65 T68 0 T56 ON ON 00000000 11110000 T58 T60 T63 T65 T68 ON 00000000 00110000 18 22 26 mA 3 3 ON ON 64 80 96 mA 0 0 ON ON V38 S63 DV1 00000000 S56 unit S68, S65, S60, S58, voltage (MSB-LSB) DV2 00110000 I C bus data Out Test Condition min typ Mag VCC2 VCC2 Point SW 2 Parameter Freq Symbol Input signal Point Signal Current drain 2 ICC21 Current drain at RGB ICC23 standby 2 Gain at 6dB for two drives G68L SG3 G65L VIN39 VIN41 SG2 G63L VIN43 SG1 G60L SG5 G58L VIN45 VIN51 SG6 G56L VIN53 SG6 Gain at 9dB for two drives G68H SG3 G65H VIN39 VIN41 SG2 G63H VIN43 SG1 G60H SG5 G58H VIN45 VIN51 SG6 G56H VIN53 SG6 LA73033M Gain at 6dB for one drive G68L SG3 in two-drive mode G65L VIN39 VIN41 SG2 G63L VIN43 SG1 G60L SG5 G58L VIN45 VIN51 SG6 G56L VIN53 SG6 Gain at 9dB for one drive G68H SG3 in two-drive mode G65H VIN39 VIN41 SG2 G63H VIN43 SG1 G60H SG5 G58H VIN45 VIN51 SG6 G56H VIN53 SG6 Output gain ratio SG3 (composite/ S) 68/65 VIN39 68/63 VIN41 SG2 No.A0646-7/24 65/63 VIN43 SG1 Continued from preceding page. Spec Out Test Condition min V18 Calculate the gain ratio of two outputs. -5 0 5 % 0 0 ON ON 00000000 V38 S63 DV1 S56 typ max S68, S65, S60, S58, unit voltage (MSB-LSB) DV2 11110000 Mag 709mVp-p 709mVp-p 709mVp-p 7MHz Measure gain of each output relative to input and calculate the change rate for gain at 100kHz. -2 -0.8 0.4 dB 0 0 ON ON 7MHz 714mVp-p 7MHz 7MHz 7MHz 7MHz 1Vp-p Measure gain of each output relative to input and calculate the change rate for gain at 100kHz. -33 -25 dB 0 T65 T63 T60 T58 T56 T60 T58 T56 T60 T58 T56 T60 T58 T56 T60 T58 T56 T60 T58 T56 Continued on next page. input. 100kHz. Measure gain of each output relative to 5.6 5.9 6.4 dB 3 3 ON OFF Measure gain of each output relative to input and calculate the change rate for gain at -0.5 -0.1 0.5 dB 0 3 ON OFF 10000000 00100000 input. Two-drive mode. Measure gain of each output relative to 5.6 6.1 6.4 dB 0 3 ON OFF 10000000 00100000 100kHz. -37 -30 dB 00001000 00110000 and calculate the change rate for gain at Measure gain of each output relative to input -2.3 -1.1 0.1 dB 0 0 ON ON 00001000 00110000 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 700mVp-p 700mVp-p 700mVp-p T68 0 1Vp-p T56 ON ON 00000000 00110000 1Vp-p T58 1Vp-p T60 1Vp-p T63 T65 1Vp-p T68 T56 00000000 00110000 T58 T60 Point Control I C bus data SW 2 Parameter Freq Symbol Input signal Point Signal Output gain ratio SG5 (component) 60/58 VIN45 60/56 VIN51 SG6 58/56 VIN53 SG6 7MHz change rate for F68L SG3 f characteristics of GAIN F65L VIN39 VIN41 SG2 F63L VIN43 SG1 F60L1 SG1 F58L1 F56L1 VIN45 VIN51 SG4 VIN53 SG4 27MHz change rate of F68H SG3 27MHz f characteristics of GAIN F65H VIN39 VIN41 SG2 27MHz 714mVp-p SG1 27MHz SG1 27MHz SG4 27MHz F63H VIN43 F60H1 V 45 IN F58H1 V 51 IN F56H1 V 53 IN SG4 27MHz 14MHz change rate for f F60L2 SG1 14MHz LA73033M characteristics of GAIN F58L2 VIN45 VIN51 SG4 14MHz F56L2 VIN53 SG4 14MHz 54MHz change rate for f SG1 54MHz characteristics of GAIN F60H2 VIN45 F58H2 VIN51 SG4 54MHz F56H2 VIN53 SG4 54MHz Gain at RGB through One G60E SG8 drive G58E SG8 G56E VIN9 VIN11 VIN73 SG8 10MHz change rate for F60E SG9 10MHz 700mVp-p f characteristics of GAIN F58E SG9 10MHz 700mVp-p at RGB through 700mVp-p 700mVp-p 700mVp-p F56E VIN9 VIN11 VIN73 SG9 10MHz 700mVp-p Gain at RGB standby One G60E SG8 drive G58E SG8 No.A0646-8/24 G56E VIN9 VIN11 VIN73 SG8 Continued from preceding page. Spec Out Test Condition min V18 Measure the pin voltage. 2.1 2.5 2.9 V 0 0 ON ON V38 S63 DV1 00000010 00000001 00000100 Measure the pin voltage with VCC = 4.75 to 5.25V 2.05 0 0 0.35 V 0 0 2.2 2.35 V 0 0 ON ON 4.1 4.4 4.7 V 0 0 ON ON ON ON 00100000 00010000 00000000 S56 typ max S68, S65, S60, S58, Freq T65 T63 T60 T58 T56 T66 T66 T66 00110000 00110000 00110000 00110000 00110000 Mag Point unit voltage Control I C bus data (MSB-LSB) DV2 00110000 SW 2 Input signal Parameter Symbol Point Signal MUTE voltage V65MD V63MD V60MD V58MD V56MD DC for SQ VSQ DC for LB VLB DC for 4 : 3 V43 Design guarantee items Spec Out Test Condition min -20 10 20 typ max V18 Difference in group delay of 7MHz relative to 100kHz of each output ns 0 V38 0 Freq 7MHz 7MHz 714mVp-p 7MHz 7MHz 1Vp-p T58 T56 T60 T58 T56 T68 T63 T60 T68 level of each output signal. Calculate the ratio in percentage of the amplitude of SIN wave on the white level relative to that of SIN wave on the black 01000000 00110000 1 2 % 0 0 ON ON 00000000 00110000 100kHz of each output Difference in group delay of 14MHz from -15 5 15 ns 0 0 ON ON 00001000 00110000 T60 7MHz 714mVp-p 7MHz 714mVp-p 1Vp-p 1Vp-p T63 T65 1Vp-p T68 Mag Point unit Control voltage SW S68, S65, S60, S58, S63 ON S56 ON I C bus data (MSB-LSB) DV1 00000000 DV2 00110000 2 Input signal Parameter Symbol Point Signal f characteristcs of GD68 SG3 LA73033M group delay at 7MHz GD65 VIN39 VIN41 SG2 (interlace) GD63 VIN43 SG1 SG1 GD60-1 VIN45 GD58-1 VIN51 SG4 GD56-1 VIN53 SG4 f characteristics of SG1 14MHz group delay at 14MHz GD60-2 VIN45 GD58-2 VIN51 1Vp-p 1Vp-p 1Vp-p SG4 14MHz 714mVp-p (progressive) GD56-2 VIN53 SG4 14MHz 714mVp-p DG DG68 SG7 3.58MHz DG63 VIN39 VIN43 SG7 3.58MHz DG60 VIN45 SG7 3.58MHz DGMIX VIN41 VIN43 SG2 3.58MHz 286mVp-p Y only 1Vp-p SG7 component No.A0646-9/24 Continued on next page. Continued from preceding page. Spec Out Test Condition min V18 Measure the difference in phase of the SIN wave on the black level of each output signal relative to that of SIN wave on the white level. 01000000 00110000 -1 0.5 1 deg 0 0 ON ON V38 S63 DV1 00000000 S56 typ max S68, S65, S60, S58, Freq 1Vp-p 1Vp-p 1Vp-p T68 T60 T63 T68 Mag Point unit voltage Control (MSB-LSB) DV2 00110000 I C bus data SW 2 Input signal Parameter Symbol Point Signal DP DP68 SG7 3.58MHz DP63 VIN39 VIN43 SG7 3.58MHz DP60 VIN45 SG7 3.58MHz DPMIX VIN41 VIN43 4MHz 4MHz 714mVp-p 4MHz 4MHz 4MHz 714mVp-p 4MHz 714mVp-p 1Vp-p T68 -79 -77 dB T63 T60 T68 -73 -71 express it in dB. dB 0 0 ON noise meter (LPF 10MHz, HPF 100kHz) and 1Vp-p 1Vp-p 1Vp-p Measure the S/ N ratio of output signal with a T56 0 0 ON T58 1Vp-p T60 outputs. 1Vp-p T63 relative to the 4MHz amplitude of other T65 of non-input route and calculate its ratio 1Vp-p T68 Measure the 4MHz component of the otput -60 -55 dB 0 0 ON SG2 3.58MHz 286mVp-p Y only SG7 1Vp-p component Crosstalk CT68 SG3 ON 00000000 00110000 CT65 VIN39 VIN41 SG2 CT63 VIN43 SG1 CT60 SG1 CT58 CT56 VIN45 VIN51 SG4 VIN53 SG4 Video S/ N ratio SN68 SG5 ON 00000000 00110000 SN63 VIN39 VIN43 SG5 SN60 VIN45 SG5 LA73033M SNMIX VIN43 SG5 ON 01000000 00110000 No.A0646-10/24 LA73033M Block Diagram and Test Circuits Y2.OUT/R OUT/C.OUT Cb.OUT/B.OUT Cr.OUT/G.OUT Cb.IN/B.IN Cr.IN/G.IN Y2.IN/R.IN Y.IN VCC (CN1) N.C 49 N.C 48 N.C 47 N.C 46 VCC (CS1) + 60 GND (CN2) VCC (CN2) Y1.OUT 61 62 + 63 64 65 66 67 + 68 69 N.C 70 N.C 71 VCC (B) 72 73 B.IN VCC (Y) GND + (CN4) 59 58 GND + (CN3) 57 56 55 N.C 54 53 GND (CN1) 52 51 50 45 44 43 GND (CS1) 42 41 REG2 40 + SYNC SEP 75 driver 75 driver 75 driver 75 driver 75 driver 75 driver S1/S2 PC_OUT pedestal CLAMP 39 pedestal CLAMP CLAMP pedestal CLAMP CLAMP CLAMP 36 CLAMP 35 Y/C MIX CLAMP 33 CTL LOGIC SERIAL DECORDER 32 SYNC SEP 31 30 29 28 SCLK SDATA GND (IC) AGCCTL1 B_OUT GND (B) Y.OUT/CV.OUT GND (Y) C.OUT/Cr.OUT/R.OUT GND (C) CV.OUT/Cb.OUT/G.OUT GND (CV) 34 AGCCTL2 VCC (IC) CSYNC.OUT CV.IN 38 EXT-RGB_SW 37 CSYNC2.OUT LPF1 LPF2 LPF1 LPF2 LPF1 LPF2 LPF1 LPF1 LPF1 6dB AMP 6dB AMP 6dB AMP 6dB/9dB AMP 6dB/9dB AMP 6dB/9dB AMP 6dB/9dB AMP 6dB/9dB AMP 6dB/9dB AMP GND (CN3) C.OUT + 10k GND (CS2) CV.OUT/Y.OUT GND (CS4) pedestal CLAMP CLAMP 0dB/6dB AMP LPF synctip CLAMP CLP PULSE GEN V.SEP pedestal CLAMP LPF 74 75 LPF SYNC SEP SYNC LPF SYNC SELECT 0dB/6dB AMP AGCAMP 0dB/3dB LPF SYNC SEP 0dB/6dB AMP SYNC LPF SYNC SELECT 27 26 25 24 Y4.IN N.C 76 77 Y3.IN N.C 78 79 Y2.IN N.C 80 AGCAMP 0dB/3dB 0dB/6dB AMP synctip synctip synctip synctip CLAMP CLAMP CLAMP CLAMP pedestal pedestal CLAMP CLAMP synctip synctip synctip synctip synctip CLAMP CLAMP CLAMP CLAMP CLAMP CLAMP CLAMP C.IN 23 22 21 REG1 CV6.IN 19 20 + VCC (CN2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Cb.IN/G.IN STAND.BY Y.IN/CV.IN Cr.IN/R.IN N.C N.C N.C CV2.IN CV3.IN N.C CV4.IN VCC (C) VCC (SY) VCC (CV) GND (SY) CV5.IN C4.IN C3.IN C2.IN No.A0646-11/24 LA73033M Pin Functions Pin No. 13 15 17 19 21 1 79 77 75 7 Pin name CV2.IN CV3.IN CV4.IN CV5.IN CV6.IN Y1.IN / CV.IN Y2.IN Y3.IN Y4.IN C2.IN I 10k 2.9V I/0 I Impe dance Clamp Form DC voltage 1.5V at 0dB 2.1V at 6dB 1.5V at AGC 1.5V at no selection 1.5V at no signal CS-REC : 1.5V Pin Explanation Recommended clamp capacitor = 0.1F. For the selected pin, keyed clamp is applied to the input so that the clamp voltage of the output signal becomes constant when the signal is provided. Diode clamp is applied to the input when there is no signal. When no pin is selected and at CS-REC, diode clamp is applied to the input regardless of whether or not the signal is provided. Recommended capacitor = 0.1F. DC is overlapped over the signal through external C connection regardless of whether there is a 5 C3.IN signal or the pin is selected or AMP-GAIN in the mode other than CS-REC. Input/Output form VCC VCC VCC 19k VCC VCC IN CLAMP PULSE 200 100k CLAMP PULSE 0.5A 50F VCC VCC VCC IN 10k 200 3 C4.IN 50F 100F 11 Cb.IN G.IN I Clamp Form For component 3.2V at 0dB 3.0V at 6dB For RGB Recommended clamp capacitor = 0.1F. For the selected signal, keyed clamp is applied to the input so that the clamp voltage of output signal becomes constant when there is a signal to pin 1. Diode clamp is applied to the input when there is no signal at pin 1 or when the pin is not selected. For RGB through, feedback clamp is applied from the output to the input. VCC VCC VCC VCC VCC 19k IN CLAMP PULSE 200 9 Cr.IN R.IN 2.2V at 0dB 2.5V at 6dB For RGB through 2.3V 1.2V at no selection 1.2V at no signal to pin 1 73 B.IN CLAMP 100k PULSE 0.5A 50F 23 CV.OUT Cb.OUT G.OUT O 4.5 0.8V for CV/ Y 2.5V for component 1.25V for RGB For chroma output 2.2V at 0dB 2.4V at 6dB The signal that has been selected and keyed clamped (excluding chroma) is amplified and output from the emitter follower. The constant current of emitter follower is 2.5mA when the built-in LPF is selected and 7.5mA when it is not selected. VCC 40 VCC 25 C.OUT Cr.OUT R.OUT OUT 27 Y.OUT CV.OUT 29 B.OUT Continued on next page. No.A0646-12/24 LA73033M Continued from preceding page. Pin No. 18 Pin name STAND -BY-SW I/0 I Impe dance 17G DC voltage Hi : 3.3V Lo : 0V Pin Explanation Normal mode when pins 18 and 38 are "L." RGB through mode when pin 18 is "L" and pin 38 is "H." RGB standby mode when pins 18 and 38 are "H." CS-REC mode when pin 18 is "H" and pin 38 EXT -RGB -SW 38 is "L." Input/Output form VCC 100F IN 8k 50k 20 SW-REG -FILT O 880 With pin 18 = L, Pin 20 : 2.5V Pin 40 : 2.0V 1With pin 18 = H, Pin 20 : 0V Pin 40 : 0V Output pin for regulator voltage in IC. S/ N improvement measures recommended by inserting a capacitor of about 470F between this pin and GND. The amplifier reference voltage on the SW side is based on the regulator voltage VCC VCC 10pF OUT 12k 10k 10k 40 DV-REG -FILT of pin 20 and that on the driver side is based on the regulator voltage of pin 40. 30 AGCCTL1 (CV) I 128M Hi : 5V Lo : 2V Center : 3.3V Pin to control gain of composite and Y signals when AGC-AMP is used. To suppress crosstalk, it is recommended to insert a noise suppressing capacitor near the pin between the pin and GND. VCC VCC IN 500 35 AGCCTL2 (Y) 20F 36 C.SYNC OUT I 480 Hi : 5V Lo : 0.3V Composite sink output pin Lo (sink) at SYNC Pin 36 can be used for detection of no-signal because LPF is applied. Pin 37 is for detection of the weak electric field. Pin 37 can be changed to V.SYNC-OUT. OUT VCC 10k 300 EXT.RES. 37 C.SYNC OUT2 Continued on next page. No.A0646-13/24 LA73033M Continued from preceding page. Pin No. 72 74 8 10 12 14 22 24 26 28 76 78 80 2 4 6 16 32 Pin name VCC (B) VCC (Y) VCC (C) VCC (SY) VCC (CV) GND (SY) GND (CV) GND (C) GND (Y) GND (B) NC NC NC NC NC NC NC SDATA I 734M Hi : 5V Lo : V Pin to enter the serial data and its clock for IIC bus. For the input waveform, refer to the SDA & SCL standard. 0V NC pins on the input SW side. It is recommended to connect this to GND on the substrate to avoid interference between input signals. P 0V Description of each pin GND on the input SW side I/0 P Impe dance 5V DC voltage Description of each pin Pin Explanation VCC on the input SW. To avoid crosstalk, it is recommended to insert a capacitor between each VCC and GND. Keep VCC always ON. Input/Output form VCC for pin 73 input VCC for input of pins 1, 79, 77, and 75 VCC for input of pins 9, 7, 5, and 3 VCC for input of pins 11, 13, 15, 17, 19, and 21 VCC for SYNC-SEP, clamp pulse GND for pin 73 input GND for input of pins 1, 79, 77, and 75 GND for input of pins 9, 7, 5, and 3 GND for pins 11, 13, 15, 17, 19, and 21 GND for SYNC-SEP, clamp pulse VCC 25A 33 SCLK IN 500 39 CV.IN I Clamp Form 2.2V at 6dB 2.3V at 9dB 1.85V at no signal Recommended capacitor = 0.1F. For the signal with input, feedback clamp is applied to the input so that the clamp voltage becomes constant. For signal without input, diode clamp is applied to the input. Pins VCC VCC 19k VCC VCC 43 Y1.IN 39 and 45 drop to 0 to 1V when not selected. IN 200 100F 45 Y2.IN R.IN 100k Continued on next page. No.A0646-14/24 LA73033M Continued from preceding page. Pin No. 41 Pin name C.IN I/0 I Impe dance 10k DC voltage 2.7V Pin Explanation Recommended capacitor = 0.1F. DC is overlapped over the signal with external C connected, regardless of the signal or no-signal and AMP-GAIN. Input/Output form VCC VCC VCC VCC IN 10k 200 150F 100F 51 Cr.IN G.IN I Clamp Form For component 2.8V at 6dB 2.7V at 9dB For RGB 2.2V at 6dB 2.3 at 9dB 1.85V at no signal Recommended capacitor = 0.1F. In the component mode, keyed clamp is applied to the input so that the pedestal of output signal becomes constant when there is a signal at pin 45. In the RGB mode, feedback clamp is applied to the input so that the output signal clamp voltage becomes constant. Diode clamp is applied to the input when there is no signal. VCC VCC VCC VCC VCC 19k IN CLAMP PULSE 200 53 Cb.IN B.IN 100k CLAMP PULSE 68 CV.OUT Y1.OUT O 4 1.3V for CV/ Y/ RGB 2.5V for component For chroma output 2.4V at 0dB 2.6V at 6dB Recommended coupling capacitor = 470F (0.1F for chroma). The signal that has passed AMP & LPF is output from the 75 driver. Two drives possible. It is recommended to provide this capacitor as near as possible to the pin to avoid VCC 30 VCC 65 C.OUT 63 Y1.OUT OUT 30 60 Y2.OUT R.OUT C.OUT interference. 58 Cr.OUT G.OUT 56 Cb.OUT B.OUT 66 C_DC OUT O 11 Hi : 4.4V Mid : 2.2V Lo : 0V Circuit to output the DC voltage of S1 and S2 standards. When using this pin, insert a resistor (driving with about 10 k per drive) between the output chroma signal after coupling and this pin, so that the DC voltage of S1 and S2 standard can be overlapped. VCC 500 1k 500 100k 100F VCC VCC OUT 300F 500 34 44 50 55 62 VCC (IC) VCC (CS1) VCC (CN1) VCC (CN2) VCC (CS2) P 5V Description of each pin VCC on the output driver side. It is recommended to insert a capacitor between each VCC and GND to avoid crosstalk. Keep VCC normally ON. VCC for input of pins 32 and 33 VCC for input of pins 39, 41, and 43 VCC for input of pins 45, 51, and 53 VCC for output of pins 60, 58, and 56 VCC for output of pins 68, 65, and 63 Continued on next page. No.A0646-15/24 LA73033M Continued from preceding page. Pin No. 31 42 52 57 59 61 64 67 69 46 47 48 49 54 70 71 Pin name GND (IC) GND (CS1) GND (CN1) GND (CN3) GND (CN4) GND (CN2) GND (CS3) GND (CS2) GND (CS4) NC NC NC NC NC NC NC 0V NC pins on the output driver side. It is recommended to connect this pin to GND on the substrate to avoid interference with the input SW side. GND for output of pin 68 GND for output of pin 65 GND for output of pins 63 GND for output of pins 60 GND for output of pin 58 GND for output of pin 56 GND for input of 45, 51, and 53 I/0 P Impe dance 0V DC voltage Description of each pin GND for input of pins 39, 41, and 43 Pin Explanation GND on the output driver side Input/Output form GND for input of pins 32 and 33 No.A0646-16/24 LA73033M Device address Gr address SW1 SW2 DR1 DR2 00000001 00000010 00000011 00000100 bit7 (MSB) INSEL3 AGC SCART CV/ S GAIN bit6 INSEL2 V.SYNC YC MIX CP GAIN bit5 INSEL1 *Res CDC2 CV/ S DRIVE bit4 LPF *Res CDC1 CP DRIVE bit3 SWGAIN1 CLPOFF1 PROG SCART YC bit2 SWGAIN2 CLPIUP GB MUTE *Res bit1 YOUT SEL TEST2 YC MUTE *Res bit0 (LSB) *Res TEST1 CP MUTE CLPOFF2 * Res means a reserved bit. Initial state SW block INSEL3 INSEL2 INSEL1 SW block input selection/mode changeover INSEL3 0 0 0 0 1 1 1 1 LPF SWGAIN1 SWGAIN2 YOUT SEL AGC V.SYNC CLPOFF1 CLPIUP TEST2 TEST1 SW block LPF SW block amplifier gain changeover 1 (for composite/ Y signal) SW block amplifier gain changeover 2 (C/ component/ RGB signal) SW block YOUT output selection SW block AGC ON/OFF SYNC output changeover Test mode (SW block input clamp OFF) Increase in SW block clamp current C-SYNC output (TEST mode) 1 : Composite 1 : ON 1 : V-SYNC output 1 : Clamp OFF 1 : Increase in the clamp current 00 : C-SYNC (Normal) 10 : Prohibition 01 : Clamp pulse 11 : Macro vision gate 0:Y 0 : OFF 0 : C- SYNC output (for detection of weak field) 0 : Clamp ON 0 : Clamp current normal 1 : +6dB (AGC used+3dB) 0 : 0dB INSEL2 0 0 1 1 0 0 1 1 1 : LPF on 1 : +6dB (AGC used+3dB) INSEL1 0 1 0 1 0 1 0 1 0 : LPF off 0 : 0dB Input selection IN1 IN1 IN2 IN3 IN4 IN5 IN6 Mode Component RGB Composite/ S Composite/ S Composite/ S Composite/ S Composite/ S Prohibition Driver block SCART YC MIX CDC2 CDC1 PROG GB MUTE YC MUTE CP MUTE CV/ S GAIN CP GAIN CV/ S DRIVE CP DRIVE SCART YC CLPOFF2 Driver block LPF changeover Driver block G/B MUTE Driver block YC MUTE Driver block component MUTE Driver block composite/ S amplifier gain Driver block component amplifier gain Driver block composite/ S output drive capacity Driver block component output drive capacity Driver block SCART YC mode changeover Test mode (driver block input clamp OFF) Driver block component mode changeover Driver block composite output selection Driver block C_DC output voltage 1 : SCART (RGB) 1 : Y/ C MIX 00 : Low (0V) 4 : 3mode 10 : High (5V) squeeze 1 : Progressive 1 : MUTE ON 1 : MUTE ON 1 : MUTE ON 1 : +9dB 1 : +9dB 1 : Two-system drive 1 : Two-system drive 1 : YC 1 : Clamp OFF 0 : Y/ Cb/ Cr 0 : Composite (Y/ C MIX OFF) 01 : Middle (2.2V) letter box 11 : Prohibition 0 : Interlace 0 : MUTE OFF 0 : MUTE OFF 0 : MUTE OFF 0 : +6dB 0 : +6dB 0 : One-system drive 0 : One-system drive 0 : RGB 0 : Clamp ON *Initial setting at power ON Gr address SW1 SW2 DR1 DR2 00000001 00000010 00000011 00000100 data 01100010 00000000 01000000 00110000 No.A0646-17/24 LA73033M Control pin function table (1) *For the serial control pin, enter 3.5 to 5V for H and 0 to 1.5V for L. *For the parallel control pin, enter 2.6 to 5V for H and 0 to 0.7V for L. *For all control pins, do not apply the voltage higher than the one applied to VCC or lower than the one applied to GND. *No control pin must be used in the OPEN state. *Values in the table are standard values. For SPEC, refer to the electrical characteristics. [Selection of the SW side input signal] Control CV (rear 1) S (rear 1) CV (rear 2) S (rear 2) CV (front) S (front) CV (tuner) Gr address 00000001 010***1* 010***0* 011***1* 011***0* 100***1* 100***0* 101***1* 101***0* CV (tuner) 110***1* 110***0* component 000***** 000***** RGB 001***** 001***** ******** CS-REC ******** ******** Gr address 00000010 ****0*00 ****0*00 ****0*00 ****0*00 ****0*00 ****0*00 ****0*00 ****0*00 ****0*00 ****0*00 ****0*00 ****0*00 ****0*00 ****0*00 ******** ******** ******** Pin 18 Standby L L L L L L L L L L L L L L H H H Pin 38 RGB through H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L L H L H L L L Input pin to be selected Pin 23 13 (CV) , 7 (C) 7 (C) , 79 (Y) 15 (CV) , 5 (C) 5 (C) , 77 (Y) 17 (CV) , 3 (C) 3 (C) , 75 (Y) 19 (CV) None 21 (CV) None 1 1(Cb) , 9 (Cr) , 1 (Y) 1 (Y) 11 (G) , 9 (R) , 1 (CV) , 73 (B) 1 (CV) Pin 15 input15 (CV) Pins 15+77 input77 (Y) Pin 77 input77 (Y) (CV) (CV) (CV) (CV) (CV) Cb G Signal to be output Pin 25 C C C C C C DC DC DC DC Cr R Pin 27 CV Y CV Y CV Y CV DC CV DC Y Y CV CV Pin 29 DC DC DC DC DC DC DC DC DC DC DC B - (Note 1) (CV) : Though a signal is output, its use is not recommended. (Note 2) DC : The DC voltage differing depending on the AMP-GAIN setting is output. (Note 3) - : Either the signal is not output or should not be used because the DC voltage is abnormal if output. [Selection of the input signal for C.SYNC OUT] Control CV (rear 1) S (rear 1) CV (rear 2) S (rear 2) CV (front) S (front) CV (tuner) Gr address 00000001 010***1* 010***0* 011***1* 011***0* 100***1* 100***0* 101***1* 101***0* CV (tuner) component RGB V.SYNC Monitor 110***1* 110***0* 000***** 001***** ******** ******** ******** ******** CS-REC ******** ******** RGB standby ******** Gr address 00000010 *0**0*00 *0**0*00 *0**0*00 *0**0*00 *0**0*00 *0**0*00 *0**0*00 *0**0*00 *0**0*00 *0**0*00 *0**0*00 *0**0*00 *1**0*00 *0**0*01 *0**0*11 ******** ******** ******** ******** Pin 18 Standby L L L L L L L L L L L L L L L H H H H Pin 38 RGB through H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/L L L L H Input pin to be selected 13 (CV) 79 (Y) 15 (CV) 77 (Y) 17 (CV) 75 (Y) 19 (CV) None 21 (CV) None 1 (Y) 1 (CV) Same as above Same as above Same as above Pin 15 input15 (CV) Pins 15 + 77 input77 (Y) Pin 77 input77 (Y) 1 (CV) Signal to be output C.SYNC C.SYNC C.SYNC C.SYNC C.SYNC C.SYNC C.SYNC C.SYNC x C.SYNC x C.SYNC C.SYNC C.SYNC Clamp pulse Macro gate pulse C.SYNC C.SYNC C.SYNC C.SYNC C.SYNC2 C.SYNC2 C.SYNC2 C.SYNC2 C.SYNC2 C.SYNC2 C.SYNC2 C.SYNC2 x C.SYNC2 x C.SYNC2 C.SYNC2 V.SYNC C.SYNC2 C.SYNC2 x x x x No.A0646-18/24 LA73033M Control pin function table (2) [SW side AMP-GAIN selection] Control Gr address 00000001 ****00** ****10** ****01** CV/ S ****11** ****00** ****10** ****01** ****11** 000*00** 000*10** 000*01** component 000*11** 000*00** 000*10** 000*01** 000*11** 001*00** 001*10** 001*01** RGB 001*11** 001*00** 001*10** 001*01** 001*11** Gr address 00000010 0***0*00 0***0*00 0***0*00 0***0*00 1***0*00 1***0*00 1***0*00 1***0*00 0***0*00 0***0*00 0***0*00 0***0*00 1***0*00 1***0*00 1***0*00 1***0*00 0***0*00 0***0*00 0***0*00 0***0*00 1***0*00 1***0*00 1***0*00 1***0*00 Pin 18 Standby L L L L L L L L L L L L L L L L L L L L L L L L Pin 38 RGB through H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L H/ L Pin 23 (Fixed at 0dB) (Fixed at 6dB) (Fixed at 0dB) (Fixed at 6dB) (AGC0dB) (AGC3dB) (AGC0dB) (AGC3dB) Fixed at 0dB Fixed at 0dB Fixed at 6dB Fixed at 6dB Fixed at 0dB Fixed at 0dB Fixed at 6dB Fixed at 6dB Fixed at 0dB Fixed at 0dB Fixed at 6dB Fixed at 6dB Fixed at 0dB Fixed at 0dB Fixed at 6dB Fixed at 6dB AMP-GAIN Pin 25 Fixed at 0dB Fixed at 0dB Fixed at 6dB Fixed at 6dB Fixed at 0dB Fixed at 0dB Fixed at 6dB Fixed at 6dB Fixed at 0dB Fixed at 0dB Fixed at 6dB Fixed at 6dB Fixed at 0dB Fixed at 0dB Fixed at 6dB Fixed at 6dB Fixed at 0dB Fixed at 0dB Fixed at 6dB Fixed at 6dB Fixed at 0dB Fixed at 0dB Fixed at 6dB Fixed at 6dB Pin 27 Fixed at 0dB Fixed at 6dB Fixed at 0dB Fixed at 6dB AGC0dB AGC3dB AGC0dB AGC3dB Fixed at 0dB Fixed at 6dB Fixed at 0dB Fixed at 6dB AGC0dB AGC3dB AGC0dB AGC3dB Fixed at 0dB Fixed at 6dB Fixed at 0dB Fixed at 6dB AGC0dB AGC3dB AGC0dB AGC3dB Pin 29 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Fixed at 0dB Fixed at 0dB Fixed at 6dB Fixed at 6dB Fixed at 0dB Fixed at 0dB Fixed at 6dB Fixed at 6dB (Note 1) Though a signal is output, its use is not recommended. (Note 2) At the Gr address = 0000 0001 of CV/S, *** does not contain 00* . [SW side LPF selection] Control LPF-ON LPF-OFF Gr address 00000001 ***1**** ***0**** Gr address 00000010 ****0*00 ****0*00 Pin 18 Standby L L Pin 38 RGB through H/ L H/ L LPF route of each output Pins 23, 25, 27, 29 Pass Through Load corresponding to each output Pins 23, 25, 27, 29 1k 330 No.A0646-19/24 LA73033M Control pin function table (3) [Driver side input signal selection] Gr Control address 00***000 CV/ S component 00***010 00***001 01***000 Y/ C-MIX component 01***010 01***001 10***000 CV/ S RGB 10***010 10***001 11***000 YC/ MIX RGB 11***010 11***001 10***000 SCART Y/ C 10***010 10***100 11***000 SCART Y/ C-MIX CV/ S RGB through SCART Y/ C RGB through Y/ C-MIX RGB through RGB standby CS-REC 11***010 11***100 *0****0* *0****1* *0****0* *0****1* *1****0* *1****1* ******** ******** Gr address ****0**0 ****0**0 ****0**0 ****0**0 ****0**0 ****0**0 ****0**0 ****0**0 ****0**0 ****0**0 ****0**0 ****0**0 ****1**0 ****1**0 ****1**0 ****1**0 ****1**0 ****1**0 ****0**0 ****0**0 ****1**0 ****1**0 *******0 *******0 ******** ******** Pin 18 Standby L L L L L L L L L L L L L L L L L L L L L L L L H H Pin 38 RGB through L L L L L L L L L L L L L L L L L L H H H H H H H L 39 (CV) 41 (C) 43 (Y1) 45 (Y2) 51 (Cr) 53 (Cb) 39 (CV) 39 (CV) 41 (C) 43 (Y1) 41 (C) 43 (Y1) 45 (Y2) 51 (Cr) 53 (Cb) 41 (C) 43 (Y1) 45 (Y2) 51 (Cr) 53 (Cb) 39 (CV) 41 (C) 43 (Y1) 39 (CV) 41 (C) 43 (Y1) 45 (R) 39 (CV) 39 (CV) 41 (C) 43 (Y1) 41 (C) 43 (Y1) 45 (R) 41 (C) 43 (Y1) 45 (R) 39 (CV) 41 (C) 43 (Y1) 41 (C) 43 (Y1) 41 (C) 43 (Y1) 41 (C) 43 (Y1) 41 (C) 43 (Y1) 41 (C) 43 (Y1) 41 (C) 43 (Y1) 39 (CV) 41 (C) 43 (Y1) 39 (CV) 41 (C) 43 (Y1) 43 (Y1) 41 (C) 43 (Y1) 41 (C) 43 (Y1) 9 (R) 9 (R) 9 (R) 9 (R) 9 (R) 9 (R) 9 (R) 11 (G) 11 (G) 11 (G) 11 (G) 11 (G) 11 (G) 11 (G) 73 (B) 73 (B) 73 (B) 73 (B) 73 (B) 73 (B) 73 (B) 51 (G) 51 (G) 53 (B) 53 (B) 51 (G) 51 (G) 53 (B) 53 (B) 51 (G) 51 (G) 53 (B) 53 (B) 45 (R) 51 (G) 51 (G) 53 (B) 53 (B) 45 (Y2) 51 (Cr) 53 (Cb) Input pin to be selected Pin 68 Pin 65 Pin 63 Pin 60 Pin 58 Pin 56 CV CV CV CV CV CV CV CV CV CV CV CV Y1 Y1 Y1 CV CV CV CV CV Y1 Y1 CV CV C DC C C DC C C DC C C DC C C DC C C DC C C DC C DC C DC Y1 DC Y1 Y1 DC Y1 Y1 DC Y1 Y1 DC Y1 Y1 DC Y1 Y1 DC Y1 Y1 DC Y1 DC Y1 DC Y2 Y2 DC Y2 Y2 DC R R DC R R DC C C C C C C R R R R R R R Cr Cr DC Cr Cr DC G G DC G G DC G G DC G G DC G G G G G G G Cb Cb DC Cb Cb DC B B DC B B DC R R DC R R DC B B B B B B B Signal to be output 00000011 00000100 (Note 1) Y1 is a Y signal for S and Y2 is a Y signal for component. (Note 2) The mute voltage described in the table of electrical characteristics is output. (Note 3) -: Either the signal is not output or should not be used because the DC voltage is abnormal if output. No.A0646-20/24 LA73033M Control pin function table (4) [Driver side AMP-GAIN selection] Control Gr address 00000011 *****000 DAC signal *****000 *****000 *****000 DAC signal RGB through RGB standby *****000 *****000 ******** Gr address 00000100 00****00 10****00 01****00 11****00 0*****00 1*****00 ******** Pin 18 Standby L L L L L L H Pin 38 RGB through L L L L H H H Pin 68 6dB 9dB 6dB 9dB 6dB 9dB Pin 65 6dB 9dB 6dB 9dB 6dB 9dB Pin 63 6dB 9dB 6dB 9dB 6dB 9dB Pin 60 6dB 6dB 9dB 9dB 6dB 6dB 6dB Pin 58 6dB 6dB 9dB 9dB 6dB 6dB 6dB Pin 56 6dB 6dB 9dB 9dB 6dB 6dB 6dB AMP-GAIN (Note 1) At SCART-YC, the gain control of chroma output is different between pin 65 and pin 60. (Note 2) -: Either the signal is not output or should not be used because the DC voltage is abnormal if output. [Driver side LPF selection] Control Gr address 0000001 ***1**** ***0**** ******** ******** Gr address 00000100 ******00 ******00 ******00 ******** Pin 18 Standby L L L H Pin 38 RGB through L L H H Pin 68 9 9 9 Pin 65 9 9 9 Pin 63 9 9 9 Pin 60 9 18 Through Through Pin 58 9 18 Through Through Pin 56 9 18 Through Through LPF cut-off frequency (MHz) Interlace Progressive RGB through RGB standby [Selection of the number of channels that can be driven by 75 driver ] Control Gr address 0000001 *****000 DAC signal *****000 *****000 *****000 ******0* DAC signal RGB through ******0* ******0* ******0* RGB standby ******** Gr address 00000100 **00***0 **10***0 **01***0 **11***0 **00***0 **10***0 **01***0 **11***0 ******** Pin 18 Standby L L L L L L L L H Pin 38 RGB through L L L L H H H H H Pin 68 1 2 1 2 1 2 1 2 Pin 65 1 2 1 2 1 2 1 2 Pin 63 1 2 1 2 1 2 1 2 Pin 60 1 1 2 2 1 1 2 2 1 Pin 58 1 1 2 2 1 1 2 2 1 Pin 56 1 1 2 2 1 1 2 2 1 Number of channels that can be driven of each output [Selection of S1 and S2 overlapping DC] Control Gr address 0000001 **00**** For S1 and S2 control **01**** **10**** **11**** Gr address 00000100 *******0 *******0 *******0 *******0 Pin 18 Standby L L L L Pin 38 RGB through H/ L H/ L H/ L H/ L Application For 4 : 3 For letter box For squeeze Prohibited Output voltage (V) 0 2.2 4.4 Pin 66 No.A0646-21/24 LA73033M Test Input Signal P-P SG.1 1H 40IRE SIN WAVE 140IRE P-P SG.2 SIN WAVE 100IRE 1H P-P SG.3 1H P-P SG.4 1H SIN WAVE 40IRE SIN WAVE 140IRE 100IRE 50IRE P-P SG.5 1H 140IRE P-P SG.6 1H P-P 40IRE SG.7 1H SIN WAVE 100IRE 140IRE 40IRE P-P SG.8 1H P-P SG.9 1H 100IRE 100IRE No.A0646-22/24 LA73033M Sample Application T56A VIN53 VIN51 VIN45 VIN43 VIN41 0.1F 75 0.1F 75 0.1F 75 0.1F 75 0.1F 75 75 75 + + + + + + 0.1F 75 + 75 S56 75 470F T58A T58 75 75 + T60 75 S58 75 470F T60A 75 75 + 75 S60 75 470F T63A 75 75 + T65 T53 + VCC2 T51 T45 T43 T41 T39 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 YOUT2 CROUT CBOUT NC CB_IN NC NC NC NC Y2_IN VCCCS1 Y1_IN VCCCN2 CR_IN VCCCN1 GNDCN4 GNDCN3 T63 61 GNDCN2 62 VCCCS2 63 YOUT1 64 GNDCS3 65 COUTD 66 C_DC 67 GNDCS2 68 CVOUT 69 GNDCS4 70 NC GNDCN1 GNDCS1 C_IN VIN39 T56 T40 + 470F + V38 T37 10k +5V + T36 10k +5V + 75 S63 75 470F T65A 75 75 + REGDV 40 CV_IN 39 EXTRGBH 38 SYNC2L 37 SYNC_L 36 AGCCTL2 35 VCCIC 34 SCL 33 SDA 32 + V35 SERIA L DATA 75 S65 75 470F 0.1F T68A T66 T68 4.7k 75 75 + 75 S68 75 470F VIN73 75 0.1F VIN75 75 0.1F VIN77 75 0.1F VIN79 75 0.1F VIN1 75 0.1F T1 + + + + + 71 NC 72 VCCB 73 B1_IN T73 + T75 VCC1 74 VCCY 75 Y4_IN 76 NC 77 Y3_IN 78 NC 79 Y2_IN T77 LA73033M GNDIC 31 AGCCTL1 30 BOUT 29 GNDB 28 YOUT 27 GNDY 26 COUT 25 GNDC 24 CVOUT 23 GNDCV 22 STDBYH REGSW GNDSY T29 V30 T27 + 100F 330 + 100F 330 + 100F 330 + 100F 330 T25 T23 80 NC CV1_IN CV2_IN NC NC NC VCCCV VCCSY C4_IN C3_IN C2_IN C1_IN VCCC Y1_IN CV3_IN CV4_IN T79 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 + T20 470F V1 8 CV5_IN CV6_IN 21 NC VIN3 VIN5 VIN7 VIN9 + + + + + + + + + + 75 0.1F 75 0.1F 75 0.1F 75 0.1F 75 0.1F 75 0.1F 75 0.1F 75 0.1F 75 0.1F 75 0.1F T3 T5 T7 T9 T11 VIN13 T13 VIN15 T15 VIN17 T17 VIN19 T19 VIN21 T21 VIN11 No.A0646-23/24 LA73033M SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of July, 2007. Specifications and information herein are subject to change without notice. PS No.A0646-24/24 |
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